The present invention relates to a method of producing a thin film semiconductor element, and more particularly to its improvement in miniaturization, price, and performance.
In recent years, progress in flat displays represented by liquid crystal display panels is remarkable.
In liquid crystal displays, active matrix liquid crystal displays having switching elements disposed in each pixel have become widespread.
In other display panels such as plasma displays, electroluminescence displays, and field emission displays, switching elements are disposed for controlling pixels.
As these switching elements, MIMs (metal-insulator-metal) and TFTs (thin-film-transistor) are employed.
TFTS, on one hand, are excellent in fast-response, but on the other, their complicated production process increases production cost, thereby arousing the need for cheaper TFTs. In addition, in display panels such as liquid crystal displays, switching elements are disposed in non-display regions unused for displaying pixels, thereby arousing the need for miniaturized TFTs in terms of high definition display. The miniaturization of TFTs is also needed for other devices in terms of highly dense packages on substrates.
A top gate type MIS (metal-insulator-semiconductor) TFT widely used in liquid crystal displays and the like is shown in FIGS. 20a and 20b. 
A TFT, which is disposed on an insulation substrate 1 composed of glass or the like via an undercoat layer 2, is provided with a semiconductor thin film 3 composed of amorphous silicon (a-Si), polycrystal silicon (p-Si), or the like. In a source region 3b and a drain region 3c of the semiconductor thin film 3, N type or P type impurity ions are implanted. When voltage is applied on a gate electrode 5a disposed above a channel region (active region) 3a of the semiconductor thin film 3 via an insulation film 4, a source electrode wiring line 8b and a drain electrode wiring line 8c are electrically connected.
The undercoat 2 prevents impurities from mixing from the substrate 1 into the semiconductor thin film 3, and is composed of silicon oxide, for example. A gate insulation film 4a is composed of silicon oxide, for example.
The gate electrode 5a is composed of a metal with a high melting point of 1000xc2x0 C. or more such as chromium in order to resist heat treatment to activate a semiconductor thin film in production process.
This TFT is produced in the following manner, for example.
First, as shown in FIG. 21a, an undercoat layer 2 and a semiconductor thin film 3 are formed on one surface of a substrate 1, and the thin film 3 is then processed into a predetermined pattern by etching using a resist layer 18 as a mask.
Next, on the semiconductor thin film 3, an insulation film 4 and a gate electrode 5a are formed. For example, as shown in FIG. 21b, the insulation film 4 composed of silicon oxide and a conductive film 5 composed of chromium are formed to cover the semiconductor thin film 3. Thereafter, the conductive film 5 is processed into a predetermined pattern by etching using a resist layer 19 as a mask, thus forming the gate electrode 5a. 
Using the formed gate electrode 5a and the insulation film 4 as masks, P type or N type impurity ions are implanted in the semiconductor thin film 3, thus forming a source region 3b and a drain region 3c, as shown in FIG. 21c. 
Note that, in the case of a TFT with an LDD (lightly-doped drain) structure, ions are further implanted into any one of the above-formed source region 3b and drain region 3c separated from the channel region 3a so that the separated region has a higher ion concentration.
In the case of a TFT with what is called an xe2x80x9coffset structurexe2x80x9d, a mask covering a periphery of the gate electrode 5a is used for the above-described ion-implanting.
Thereover, an insulation film 6 composed of silicon oxide, for example, is formed, and in this insulation film 6, a contact hole 6a for connecting the source region 3b and drain region 3c of the thin film 3 to external wiring lines is formed by etching using resist layers 21 as masks.
Thereover, after forming the contact hole 6a, a conductive film 8 composed of aluminum, for example, is formed as shown in FIG. 21e, and a source electrode wiring line 8b, a drain electrode wiring line 8c, and the like are formed by etching using resist layers 20 as masks, thereby obtaining the TFT shown in FIGS. 20a and 20b. 
Thereover, in an actual device, other signal wiring lines such as a line to connect a source wiring line to a signal source and the like are further formed via an insulation film in a similar manner.
Generally, elements are designed to avoid variations in the properties of finished products caused by errors and variations in production processes. Design margins for stable production may be one of factors to prevent the miniaturization of elements. In the production of the above-described conventional TFT, such designs are indispensable as to avoid size variations of masks used in etching and ion-implanting, and mispositioning of masks and substrates (or thin films to be processed). For example, when forming a contact hole, they need to be considered to secure a sufficient distance between a place where the contact hole is disposed and a gate electrode. Accordingly, conventional TFTs have been forced to be made longer in their longitudinal directions than preferable designs in terms of functionality.
The above-described design margins may also reduce the properties of elements and devices using the elements. For example, distances between edge portions of a channel region and source/drain electrode wiring lines, in other words, a distance between a gate electrode and a contact hole has great effect on electric current strength between the source/drain electrode wiring lines in the on-state of an element. It is difficult to reduce the electric resistance of source/drain regions down to the levels of metal wiring lines, even if impurity concentrations of the regions are increased. In addition, extreme increase in the impurity concentrations of the regions makes the element less reliable. Thus, the design margin between the gate electrode and the contact hole increases source/drain electric resistance, thereby reducing electric current in the on-state of the element.
It is an object of the present invention to solve the foregoing problems and provide a thin film semiconductor element which is small in area with high on-current enough to be suitable for the power saving, miniaturization, and high definition display of a device. It is another object of the present invention to provide such excellent thin film semiconductor element at low price.
The present invention reduces an element area to a great extent by reducing source/drain areas of a transistor. Also, the present invention increases on-current of the element by extensively reducing distances between a gate electrode and source/drain electrodes (wiring lines).
Moreover, the present invention simplifies production process of an element.
According to the present invention, an outer shape of a semiconductor thin film is processed, and regions (a channel region, a source region, and a drain region) of the semiconductor thin film are formed by using other element components as masks such as a gate electrode. Specifically, the gate electrode and the like are formed first, and then the semiconductor thin film is self-aligningly processed in correspondence with shapes of those components Thus, design margins required of the production of conventional thin film semiconductor elements are made less to the greatest possible degree, and a thin film semiconductor element which is small in size and excellent in properties is realized. In addition, production process is simplified such as to decrease the number of masks required.
In the production of a thin film semiconductor element of the present invention, an ion-implanted region is formed by implanting impurity ions into a predetermined region of a semiconductor thin film using, as a mask, a gate electrode overlapped on the thin film via an insulation layer. The semiconductor thin film is then processed into a predetermined shape by etching using, as masks, previously formed other element components such as the gate electrode. It is needless to form a mask used only for processing the semiconductor thin film so that a source region and a drain region both implanted with the impurity ions are disposed to face each other sandwiching a channel region (active region).
A thin film semiconductor is produced by the following method, for example.
First, a semiconductor thin film to be an active region is formed on an insulation substrate, and thereon, a first insulation film, a conductive film, and a second insulation film are formed in this order.
Next, the conductive film is processed into a predetermined pattern by etching, thereby forming a gate electrode. On such occasion, the second insulation film formed on the conductive film is processed into a similar pattern.
For example, on a surface of the second insulation film, a first resist layer having a predetermined pattern is formed, and thereafter, the second insulation film and a first conductive film are etched using the first resist layer as a mask, whereby the first conductive film is processed into the gate electrode. Note that, if the first insulation film below the conductive film is processed simultaneously, a gate insulation layer is formed as well between the gate electrode and the semiconductor thin film. After the etching, the first resist layer is removed.
Next, N type or P type impurity ions are implanted into the semiconductor film formed under the gate electrode using the gate electrode as a mask. Here, in the semiconductor thin film, a region covered with the gate electrode is processed into a channel region of a transistor. Impurities are implanted into a predetermined region of the semiconductor thin film through the first insulation layer or directly using the gate electrode as a mask. Note that, in order to avoid a source/drain short circuit of a transistor to be formed, second resist layers are preferably formed for covering edge regions of the channel region of the semiconductor thin film so as to serve as masks along with the gate electrode. After ion-implanting, the second resist layers are removed.
When an insulation film covering a surface of the semiconductor thin film is removed in advance of impurity ion-implanting into the thin film, impurity ion-implanting with high efficiency is made possible with low energy compared with impurity ion-implanting through the insulation film. In addition, impurity ions can be implanted in a concentrated manner easily. Amount variations of implanted ions caused from uneven film thickness of an insulation film may be avoided, making it possible to obtain a thin film semiconductor device with good uniformity in electric properties.
Next, a frame-shaped insulation wall to cover side surfaces of the gate electrode is formed. For example, an insulation film is formed uniformly on the substrate and then removed except for portions around the gate electrode by anisotropic etching. Portions of the insulation film around the gate electrode are thicker than flat regions, in other words, a region in which the gate electrode is disposed and a region in which the first insulation layer (or the semiconductor thin film) is exposed. Accordingly, by properly adjusting conditions of subsequent etching, it is made possible that an insulator remains only around the gate electrode.
After forming the insulation wall, a second conductive film is formed to cover one surface of an insulation substrate having formed thereon the semiconductor thin film, and the second conductive film is then processed into wiring lines connected to a source region and a drain region by etching using resist layers having predetermined patterns as masks. In this etching, since the gate electrode and the insulation wall also serve as masks, the semiconductor thin film disposed under them is processed into a predetermined shape having the source region and the drain region.
After forming the source electrode and the drain electrode, a third insulation film is formed all over the substrate. Next, an aperture portion is formed in a region of the third insulation film covering the gate electrode, and in a region including this aperture portion, other wiring lines connected to the gate electrode such as a scanning signal line are formed, thereby obtaining a semiconductor element.
Note that, when implanting impurity ions after forming the insulation wall, the impurity ions are not implanted into a region of the semiconductor thin film covered by the insulation wall, thereby obtaining a thin film semiconductor with what is called an offset structure.
When, after forming the insulation wall but before forming the second conductive film using the gate electrode and the insulation wall as masks, a same type of impurity ions as that used in the previous ion-implanting are implanted into the semiconductor thin film in order to form sub regions with higher impurity ion concentrations in the semiconductor thin film, whereby a semiconductor element with what is called an LDD (lightly-doped drain) structure is obtained.
What is called a CMOS transistor using a P transistor and an N transistor in pairs can be produced by a same method as that described above. Specifically, when impurity ion-implanting is carried out on one transistor, such masks may be used as to have patterns to cover regions of the other transistor to be implanted with impurity ions (or a region which has already been implanted).
Preferably, after forming the third insulation film, heat treatment is carried out on the semiconductor thin film for activation.
A thin film semiconductor element is also produced by the following method.
First, similarly to the above, a semiconductor thin film, a first insulation film, a first conductive film, and a second insulation film are formed in this order. Next, the conductive film is processed into a predetermined pattern by etching, thereby forming a gate electrode. On such occasion, the second insulation film formed on the conductive film is processed into a similar pattern.
For example, after forming first resist layers having predetermined patterns on a surface of the second insulation film, the second insulation film and the first conductive film are etched using the first resist layer. Note that, if the first insulation film formed under the conductive film is processed simultaneously, a gate insulation layer is formed between the gate electrode and the semiconductor thin film. After the etching, the first resist layers are removed.
Next, impurity ions are implanted into the semiconductor thin film through the first insulation film or directly using the gate electrode as a mask. Note that, in order to avoid a source/drain short circuit of a transistor to be formed, second resist layers are preferably formed for covering edge portions of a channel region of the semiconductor thin film to serve as masks along with the gate electrode. After ion-implanting, the second resist layers are removed.
Next, similarly to the above, a frame-shaped insulation wall to cover side surfaces of the gate electrode is formed. Specifically, an insulation film is formed uniformly on the substrate and then removed except for portions around the gate electrode by anisotropic etching. On such occasion, regions of the semiconductor thin film under an insulator formed to connect to the gate electrode and side surfaces thereof are removed by etching, and the thin film is divided into pieces to be used in an element. Here, when the first insulation film is not processed into a gate insulation film, regions of the first insulation film which are exposed and not covered by the masks are removed simultaneously, thus forming the gate insulation film.
By the above etching, the semiconductor thin film is processed, whereby edge surfaces thereof are exposed. Wiring lines connected to a source electrode and a drain electrode are formed to contact with the exposed end surfaces of the processed semiconductor thin film which are implanted with impurity ions.
After forming the source electrode and the drain electrode, a third insulation film is formed all over the substrate. Next, an aperture portion is formed in a region of the third insulation film covering the gate electrode, and in a region including this aperture portion, other wiring lines connected to the gate electrode such as a scanning signal line are formed, thus obtaining a semiconductor element.
The production method of the present invention can be applied to a semiconductor element with what is called an LDD (lightly-doped drain) structure. Generally, when etching is carried out using a mask, one side of an obtained pattern next to the mask has approximately a same outer shape as that of the mask, but the other side of the obtained pattern has a larger outer shape than that of the mask. Accordingly, one side (upper side) of a pattern of a semiconductor thin film next to an insulation wall has approximately a same outer shape as that of the insulation wall, but the other side (lower side) of the pattern has a larger outer shape than that of the wall, the both sides being obtained by forming a frame-shaped insulation wall to surround a gate electrode and by processing the semiconductor thin film into a predetermined pattern. Using the insulation wall and the gate electrode as masks, a same type of impurities as that implanted in the previous are implanted into regions of the semiconductor thin film which have already been implanted with the impurity ions and are not covered by the insulation wall so that impurity-ion concentrations of the regions are made higher than those of regions covered by the insulation wall. Thus, an LDD structure is obtained.
When, after forming the insulation wall to surround the gate electrode, ions are implanted into the semiconductor thin film using the insulation wall and the gate electrode as masks, whereby a thin film semiconductor element with an offset structure is obtained.
In the case where a P channel semiconductor element and an N channel semiconductor element are formed on a same substrate such as in a CMOS transistor, second resist layers with different patterns from each other may be used when implanting P type and N type impurities.
A thin film semiconductor element of the present invention comprises:
A semiconductor thin film having in a pair of edge portions thereof a source region and a drain region both implanted with impurity ions;
An insulation film to cover one surface of the semiconductor thin film;
A gate electrode disposed to counter a region of the semiconductor thin film via the insulation, the region not being implanted with the impurity ions;
A frame-shaped insulation wall to cover a periphery of the gate electrode;
A source wiring line connected to the source region; and
A drain wiring line connected to the drain electrode;
A whole of the semiconductor thin film is covered by the gate electrode, the insulation wall, the source wiring line, and the drain wiring line.
Preferably, a shape of the semiconductor thin film is substantially equal to an outer shape of a combination of the gate electrode, the insulation wall, the source wiring line, and the drain wiring line.
Another thin film semiconductor element of the present invention comprises:
A semiconductor thin film having in a pair of edge portions thereof a source region and a drain region both implanted with impurity ions;
A frame-shaped insulation wall to cover a periphery of the semiconductor thin film;
An insulation film to cover one surface of the semiconductor thin film;
A gate electrode disposed to counter a region of the semiconductor thin film via the insulation film, the region not being implanted with the impurity ions;
A source wiring line connected to the source region; and
A drain wiring line connected to the drain electrode; and
A shape of the semiconductor thin film is substantially equal to an outer shape of the insulation wall;
The source wiring line and the drain wiring line are connected, for example, to edge surfaces of the semiconductor thin film in which the source region and the drain region are formed.
A thin film semiconductor element of the present invention is used as a switching element for controlling operations of light control means and light emission means in liquid crystal display panels, organic EL display panels, display panels, and the like.
Note that the present invention has a utility particularly for what is called a top-gate semiconductor element in which a gate electrode is disposed above a semiconductor thin film, but the present invention also has a utility for what is called a bottom-gate semiconductor element in which a gate electrode is disposed under a semiconductor thin film.
Impurities for forming a source region and a drain region are implanted into a semiconductor thin film by, for example, a plasma doping method. In addition, a source region and a drain region can also be formed by a method such that, after the introduction of impurities into wiring lines connected to the regions, the impurities are diffused into the semiconductor thin film by heat treatment.
As impurities for an N channel transistor, phosphorous is used, and as impurities for a P channel transistor, boron is used, for example.
According to the present invention, since a thin film semiconductor element excellent in fast-response can be obtained, it is made possible to produce a display panel for a large screen by using the element as a switching element.